NXP PN5120A0HN1/C2,151 Datasheet & Stock

Most broadly adopted NFC frontend - powering more than 10 billion NFC transactions per year.




Fast and cost-efficient NFC design start-up

Highly integrated analogue circuitry to demodulate and decode responses

Integrated RF level detector and integrated data mode detector

Supports ISO/IEC 14443 A/MIFARE and supports ISO/IEC 14443 B read/write modes

Supports MIFARE Classic encryption in reader/writer mode

Contactless communication according to the FeliCa scheme at 212Kbit/s and 424Kbit/s

Supported host interfaces and flexible interrupt modes

FIFO buffer handles 64byte send and receive

Hard reset with low power function, power-down mode per software

CRC coprocessor, programmable I/O pins, internal self-test, programmable timer